ADE7854/ADE7858/ADE7868/ADE7878
Table 41. PHSTATUS Register (Address 0xE600)
Data Sheet
Bit
Location
2:0
3
4
5
8:6
9
10
11
12
13
14
15
Bit Mnemonic
Reserved
OIPHASE[0]
OIPHASE[1]
OIPHASE[2]
Reserved
OVPHASE[0]
OVPHASE[1]
OVPHASE[2]
VSPHASE[0]
VSPHASE[1]
VSPHASE[2]
Reserved
Default Value
000
0
0
0
000
0
0
0
0
0
0
0
Description
Reserved. These bits are always 0.
When this bit is set to 1, Phase A current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, Phase B current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, Phase C current generates Bit 17 (OI) in the STATUS1 register.
Reserved. These bits are always 0.
When this bit is set to 1, Phase A voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase B voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase C voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase A voltage generates Bit 16 (SAG) in the STATUS1 register.
When this bit is set to 1, Phase B voltage generates Bit 16 (SAG) in the STATUS1 register.
When this bit is set to 1, Phase C voltage generates Bit16 (SAG) in the STATUS1 register.
Reserved. This bit is always 0.
Table 42. PHNOLOAD Register (Address 0xE608)
Bit
Location
0
Bit Mnemonic
NLPHASE[0]
Default Value
0
Description
0: Phase A is out of no load condition based on total active/reactive powers.
1: Phase A is in no load condition based on total active/reactive powers. Bit set together with
Bit 0 (NLOAD) in the STATUS1 register.
The ADE7854 no load condition is based only on the total active powers.
1
NLPHASE[1]
0
0: Phase B is out of no load condition based on total active/reactive powers.
1: Phase B is in no load condition based on total active/reactive powers. Bit set together with
Bit 0 (NLOAD) in the STATUS1 register.
The ADE7854 no load condition is based only on the total active powers.
2
NLPHASE[2]
0
0: Phase C is out of no load condition based on total active/reactive powers.
1: Phase C is in no load condition based on total active/reactive powers. Bit set together with
Bit 0 (NLOAD) in the STATUS1 register.
The ADE7854 no load condition is based only on the total active powers.
3
FNLPHASE[0]
0
0: Phase A is out of no load condition based on fundamental active/reactive powers. This bit
is always 0 for ADE7854 , ADE7858 , and ADE7868 .
1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
4
FNLPHASE[1]
0
0: Phase B is out of no load condition based on fundamental active/reactive powers. This bit
is always 0 for ADE7854 , ADE7858 , and ADE7868 .
1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
5
FNLPHASE[2]
0
0: Phase C is out of no load condition based on fundamental active/reactive powers. This bit
is always 0 for ADE7854 , ADE7858 , and ADE7868 .
1: Phase C is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
6
VANLPHASE[0]
0
0: Phase A is out of no load condition based on apparent power.
1: Phase A is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
7
VANLPHASE[1]
0
0: Phase B is out of no load condition based on apparent power.
1: Phase B is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
8
VANLPHASE[2]
0
0: Phase C is out of no load condition based on apparent power.
1: Phase C is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
15:9
Reserved
000 0000
Reserved. These bits are always 0.
Rev. H| Page 90 of 100
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